ROCOF-Based Islanding Detection in Low-Inertia Grids (B.Tech Project).exe
Led the development of a hybrid SDFT-SVM system for ROCOF-based islanding detection in low-inertia microgrids. Designed and simulated a Sliding DFT algorithm in MATLAB/Simulink, improving noise immunity and reducing detection latency. Built an SVM-based feature extraction and classification pipeline that eliminated the Non-Detection Zone (NDZ). Modeled a two-stage architecture for real-time DSP/FPGA deployment with validated ROCOF thresholds.
Role
Team Lead / Core Contributor
Duration
6 Months
Team
5
v1.0.0 Stable
System_Features.logREAD ONLY
- 1Hybrid SDFT-SVM Architecture: Combines advanced signal processing with supervised machine learning for highly accurate passive relay protection.
- 2Real-Time Feature Extraction: Converts raw signal outputs into multi-dimensional feature vectors (Δf, ROCOF, Δθ, THD) on the fly.
- 3Two-Stage ML Deployment: Supports offline training on simulated fault datasets and real-time classification on live data streams.
- 4Mathematical Validation: Analytically verified Swing Equations, NDZ boundaries, and threshold limits for high IBR penetration microgrids.
Dependencies.json
MATLABSimulinkSupport Vector Machine (SVM)Machine LearningSignal ProcessingData Classification
⚠ CRITICAL_ERRORS.log
- [ERROR_100]: Standard frequency estimation methods (Zero-Crossing, FFT) suffered from high latency and poor noise immunity in low-inertia grids.
- [ERROR_101]: Traditional passive relays had a significant Non-Detection Zone (NDZ) where critical islanding conditions went completely unnoticed.
- [ERROR_102]: Processing highly non-linear grid transient data in real-time required a lightweight yet highly accurate classification model suitable for embedded hardware.
✔ PATCH_NOTES.txt
- [FIX_APPLIED]: Implemented a Sliding DFT (SDFT) algorithm to drastically improve frequency estimation speed and resistance to signal noise.
- [FIX_APPLIED]: Integrated an RBF-kernel Support Vector Machine (SVM) to intelligently classify complex transient data, effectively shrinking the NDZ to zero.
- [FIX_APPLIED]: Designed a streamlined, two-stage machine learning pipeline optimized for eventual deployment on embedded DSP/FPGA systems to ensure rapid, real-time inference.
Unit_Roster.dat
COUNT: 3
